Technical Field
The present disclosure relates to electrically erasable and programmable non-volatile memories (EEPROM). The present disclosure relates more particularly to a non-volatile memory, comprising memory cells each comprising a floating-gate transistor and a select transistor gate.
Description of the Related Art
Several solutions have been implemented to miniaturize such memory cells. Thus, the memory cells have been grouped together in pairs of so-called “twin” memory cells to share a single select transistor.
FIG. 1 is a wiring diagram of a pair of memory cells C11, C12 sharing a select transistor, belonging to two adjacent word lines W<i>, W<i+1> of a memory array. The memory cells C11, C12 are read- and write-accessible through a bit line BL<j>, a common select line SL<i> and control gate lines CGL<i>, CGL<i+1>. Each memory cell C11, C12 comprises a floating-gate transistor FGT. The control gate CG of the transistor FGT of each cell C11, C12 is connected to the control gate line CGL<i> through a contact C4. The drain regions of the transistors FGT are connected to a bit line BL through contacts C1. Furthermore, each floating-gate transistor FGT has its source terminal coupled to a source line CSL through a respective select transistor ST. The select transistors ST share a same select control gate SGC. The two memory cells C11, C12 are referred to as “twins” due to the fact that they share the same select control gate SGC and the same bit line BL. The common control gate SGC is connected to the select line SL<i> common to the two memory cells through a contact C3. The channel regions of the transistors FGT, ST are at the electric potential of the well PW, as represented by dotted lines. Finally, the source line CSL may be connected through a contact C5 to a general source line produced in a level of metal.
It has also been proposed to vertically arrange the select transistor. FIG. 2 is a schematic cross-section of two twin memory cells C11, C12, sharing a vertical select transistor gate SGC, common to two twin memory cells. The memory cells C11, C12 are produced in a P-type conductivity well PW. The well PW is formed in a semiconductor wafer WF. The well PW is isolated from the rest of the wafer WF by an N-doped isolation layer n0 surrounding the entire well. Each memory cell C11, C12 comprises a floating-gate transistor FGT and a select transistor ST. Each floating-gate transistor FGT comprises a drain region n1, a source region n2, a floating gate FG, a state control gate CG, and a channel region CH1 extending beneath the floating gate FG between the drain n1 and source n2 regions. The vertical selection gate SGC is embedded in the substrate PW and isolated from the latter by a layer of gate oxide D3, for example made of silicon dioxide SiO2, forming the gate oxide of the select transistor ST. The region n2 extends along an upper edge of the embedded vertical gate SGC. The gate SGC reaches the region n0 forming a source region n0 common to the select transistors ST, and thus forms a source line CSL of the select transistors ST. Each select transistor ST thus comprises a drain region common to the source region n2 of the floating-gate transistor FGT of its cell, the common source region n0, and a channel region CH2 extending vertically along the gate SGC between the drain n2 and source n0 regions.
The regions n1, n2 are generally formed by N-doping of the substrate PW. The floating gates FG are generally made of level-1 polycrystalline silicon, or “poly1”, and are formed on the substrate PW through a layer of gate oxide D1. The state control gates CG are generally made of level-2 polycrystalline silicon, or “poly2”. Each state control gate CG is formed on one of the floating gates FG previously covered with a layer of gate oxide D2. The gate SGC is formed in a trench filled with level-0 polycrystalline silicon, or “poly0”, isolated from the substrate by the layer of gate oxide D3. Depending on the manufacturing method chosen, the conducting trench forming the gate SGC may not have any electrical discontinuity. It may then be used directly as word line WL.
The two memory cells C11, C12 are covered with a dielectric insulating material D0, which may also be silicon dioxide SiO2. The drain regions n1 of the floating-gate transistors FGT are coupled to a same bit line BL through a contact C1 passing through the insulating material D0.
Such memory cells are channel-erased or programmed, i.e., by putting the substrate to a positive erase voltage or negative programming voltage causing electric charges to be extracted from their floating gates or electric charges to be injected into their floating gates, by Fowler Nordheim effect or by hot electron injection.
More particularly, a memory cell is erased by combining the positive voltage applied to the substrate with a negative voltage applied to the control gate CG of its floating-gate transistor, while the control gate of the floating-gate transistor of the twin memory cell receives a positive erase-inhibit voltage preventing it from being simultaneously erased.
Similarly, a memory cell is programmed by combining a negative voltage applied to the bit line BL and to the substrate PW, with a positive voltage applied to the control gate CG of its floating-gate transistor, while the control gate of the floating-gate transistor of the twin memory cell receives a negative program-inhibit voltage preventing it from being simultaneously programmed.
Finally, a memory cell is read by applying a positive voltage to the control gate of its floating-gate transistor, as well as a positive voltage to the corresponding bit line, while the twin memory cell, which is connected to the same bit line, receives on its control gate a negative read-inhibit voltage preventing it from being simultaneously read.
Furthermore, for the sake of miniaturization in particular, the technology of transistors with a thin film of Fully-Depleted Silicon On Insulator (FDSOI) has been developed. This technology has several decisive advantages for future generations of technology. First of all, thanks to the use of a thin film of silicon, the electrostatic control via the gate of the channel of CMOS-type transistors is much improved compared to that of a conventional transistor produced on a massive silicon substrate. This excellent control enables, on one hand, the performance/consumption compromise of integrated circuits to be improved, and on the other hand, offers the FDSOI technology high potential for miniaturization. Then, compared to the FinFET technologies (Fin-Shaped Field Effect Transistor), which also have a very good electrostatic control, the FDSOI technology represents a disruptive technology that is easier to be produced, the transistor being planar with an architecture very similar to that of conventional technologies. Therefore the manufacturing methods are much simpler.
It is thus desirable to produce non-volatile memory cells in an FDSOI-type substrate in which logic circuits are produced based on CMOS transistors. It is also desirable to further miniaturize the non-volatile memory cells and to simplify the control of such memory cells.